The Mini-Robot Khepera as a Foraging Animate: Synthesis and Analysis of Behaviour

Löffler A, Klahold J, Rückert U. The Mini-Robot Khepera as a Foraging Animate: Synthesis and Analysis of Behaviour. In: Rückert U, Sitte J, Witkowski U, eds. Proceedings of the 5th International Heinz Nixdorf Symposium: Autonomous Minirobots for Research and Edutainment (AMiRE01). Vol 97. Paderborn, Germany: Heinz Nixdorf Institut, Universität Paderborn; 2001: 93-130.The work presented in this paper deals with the development of a methodology for resource-efficient behaviour synthesis on autonomous systems. In this context, a definition of a maximal problem with respect to the resources of a given system is introduced. It is elucidated by means of an exemplary implementation of the solution to such a problem using the mini-robot Khepera as the experimental platform. The described task consists of exploring an unknown and dynamically changing environment, collecting and transporting objects, which are associated with light-sources, and navigating to a home-base. The critical point is represented by the accumulated positioning errors in odometrical path-integration due to slippage. Therefore, adaptive sensor calibration using a specific variant of Kohonen’s algorithm is applied in two cases to extract symbolic, e.g. geometric, information from the sub-symbolic sensor data, which is used to enhance position control by landmark mapping and orientation. In order to successfully handle the arising complex interactions, a heterogeneous control-architecture based on a parallel implementation of basic behaviours coupled by a rule-based central unit is proposed

Benchmarking of Neuromorphic Hardware Systems

Ostrau C, Klarhorst C, Thies M, Rückert U. Benchmarking of Neuromorphic Hardware Systems. In: Neuro-inspired Computational Elements Workshop (NICE ’20), March 17–20, 2020, Heidelberg, Germany. International Conference Proceeding Series (ICPS). Association for Computing Machinery (ACM); 2020.With more and more neuromorphic hardware systems for the accel- eration of spiking neural networks available in science and industry, there is a demand for platform comparison and performance esti- mation of such systems. This work describes selected benchmarks implemented in a framework with exactly this target: independent black-box benchmarking and comparison of platforms suitable for the simulation/emulation of spiking neural networks

Teleworkbench: Validating Robot Programs from Simulation to Prototyping with Minirobots (Demonstration)

Tanoto A, Werner F, Rückert U, Li H. Teleworkbench: Validating Robot Programs from Simulation to Prototyping with Minirobots (Demonstration).This paper describes a Demo showing the role of the Teleworkbench in the validation process of a multi-agent system, e.g., a traffic management system. In the Demo, we show the capability of the Teleworkbench in seamlessly bridging the simulation and experimentation with real robots. During experiments, important information is logged for analysis purpose. Additionally, a graphical user interface enables geographically distributed users to perform some levels of interactivity, e.g., watch the video or command the robots

Comparing Neuromorphic Systems by Solving Sudoku Problems

Ostrau C, Klarhorst C, Thies M, Rückert U. Comparing Neuromorphic Systems by Solving Sudoku Problems. In: Conference Proceedings: 2019 International Conference on High Performance Computing & Simulation (HPCS). Piscataway, NJ: IEEE; Accepted.In the field of neuromorphic computing several hardware accelerators for spiking neural networks have been introduced, but few studies actually compare different systems. These comparative studies reveal difficulties in porting an existing network to a specific system and in predicting its performance indicators. Finding a common network architecture that is suited for all target platforms and at the same time yields decent results is a major challenge. In this contribution, we show that a winner-takes-all inspired network structure can be employed to solve Sudoku puzzles on three diverse hardware accelerators. By exploring several network implementations, we measured the number of solved puzzles in a set of 100 assorted Sudokus, as well as time and energy to solution. Concerning the last two indicators, our measurements indicate that it can be beneficial to port a network to an analogue hardware system

Teleworkbench: An Analysis Tool for Multi-Robotic Experiments

Tanoto A, Du JL, Witkowski U, Rückert U. Teleworkbench: An Analysis Tool for Multi-Robotic Experiments. In: Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), 19th World Computer Congress (WCC). Santiago, Chile; 2006.This paper presents a tool, one component of the Teleworkbench system, for analyzing experiments in multi-robotics. The proposed tool combines the video taken by a web cam monitoring the field where the experiment runs and some computer generated visual objects representing important events and information as well as robots’ behavior into one interactive video based on MPEG-4 standard. Visualization and data summarization enables the developer to quickly grasp a situation, whereas the possibility of scrolling through the video and selectively activating information helps him analyzing interesting events in depth. Because of the MPEG-4 standard used for the output video, the analysis process can be done in a wide range of platforms. This trait is beneficial for education and research cooperation purposes

Bidirectional UWB Localization: A Review on an Elastic Positioning Scheme for GNSS-deprived Zones

A bidirectional Ultra-Wideband (UWB) localization scheme is one of the three widely deployed design integration processes ordinarily destined for time-based UWB positioning systems. The key property of the bidirectional UWB localization is its ability to serve both the navigation and tracking assignments on-demand within a single localization scheme. Conventionally, the perspective of navigation and tracking in wireless localization systems is viewed distinctly as an individual system because different methodologies were required for the implementation process. The ability to flexibly or elastically combine two unique positioning perspectives (i.e., navigation and tracking) within a single scheme is a paradigm shift in the way location-based services are observed. Thus, this article addresses and pinpoints the potential of a bidirectional UWB localization scheme. Regarding this, the complete system model of the bidirectional UWB localization scheme was comprehensively described based on modular processes in this article. The demonstrative evaluation results based on two system integration processes as well as a SWOT (strengths, weaknesses, opportunities, and threats) analysis of the scheme were also discussed. Moreover, we argued that the presented bidirectional scheme can also be used as a prospective topology for the realization of precise location estimation processes in 5G/6G wireless mobile networks, as well as Wi-Fi fine-time measurement-based positioning systems in this article.Comment: 30 pages, 12 figure

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs

Compiler-Driven Reconfiguration of Multiprocessors

Hussmann M, Thies M, Kastens U, Purnaprajna M, Porrmann M, Rückert U. Compiler-Driven Reconfiguration of Multiprocessors. In: Proceedings of the Workshop on Application Specific Processors (WASP) 2007. 2007.Multiprocessors enable parallel execution of a single large application to achieve a performance improvement. An application is split at instruction, data or task level (based on the granularity), such that the overhead of partitioning is minimal. Parallelization for multiprocessors is mostly restricted to a fixed granularity. Reconfiguration enables architectural variations to allow multiple granularities of operation within a multiprocessor. This adaptability optimizes resource utilization over a fixed organization. Here, a unified hardware-software approach to design a reconfigurable multiprocessor system called QuadroCore is presented. In our holistic methodology, compiler-driven reconfiguration selects from a fixed set of modes. Each mode relies on matching program analysis to exploit the architecture efficiently. For instance, a multiprocessor may adapt to different parallelization paradigms. The compiler can determine the best execution mode for each piece of code by analyzing the parallelism in a program. A fast, singlecycle, run-time reconfiguration between these predetermined modes is enabled by executing special instructions which switch coarse-grained components like instruction decoders, ALUs and register banks. Performance is evaluated in terms of execution cycles and achieved clock frequency. First results indicate suitability especially in audio and video processing applications

Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs

Pilz S, Porrmann F, Kaiser M, Hagemeyer J, Hogan JM, Rückert U. Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs. Algorithms. 2020;13(2): 47.This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison. Modern applications which involve comparisons across large data sets—such as large sequence sets in molecular biology—are by their nature computationally intensive. In this work, we present a scalable FPGA-based system architecture to accelerate the comparison of binary strings. The current architecture supports arbitrary lengths in the range 16 to 2048-bit, covering a wide range of possible applications. In our example application, we consider DNA sequences embedded in a binary vector space through Locality Sensitive Hashing (LSH) one of several possible encodings that enable us to avoid more costly character-based operations. Here the resulting encoding is a 512-bit binary signature with comparisons based on the Hamming distance. In this approach, most of the load arises from the calculation of the O ( m ∗ n ) Hamming distances between the signatures, where m is the number of queries and n is the number of signatures contained in the database. Signature generation only needs to be performed once, and we do not consider it further, focusing instead on accelerating the signature comparisons. The proposed FPGA-based architecture is optimized for high-throughput using hundreds of computing elements, arranged in a systolic array. These core computing elements can be adapted to support other string comparison algorithms with little effort, while the other infrastructure stays the same. On a Xilinx Virtex UltraScale+ FPGA (XCVU9P-2), a peak throughput of 75.4 billion comparisons per second—of 512-bit signatures—was achieved, using a design with 384 parallel processing elements and a clock frequency of 200 MHz. This makes our FPGA design 86 times faster than a highly optimized CPU implementation. Compared to a GPU design, executed on an NVIDIA GTX1060, it performs nearly five times faster